Configurations for data ports at digital interface for multiple data converters

ABSTRACT

A data converter includes N analog-to-digital converters (ADCs) to sample multiple analog signals in response to an input clock to produce N signal samples per sample period. For each sample period, the bits of the N signal samples are multiplexed to M sets of multiplexed bits where 1&lt;M&lt;N. There are K bits in each multiplexed data set, where K equals the number of bits per sample multiplied by N then divided by M. A data clock is provided having a data clock frequency that substantially equals the input clock frequency multiplied by K. The M sets of multiplexed bits are serialized and provided to M data ports at the data clock frequency for transfer across the digital interface. This abstract does not limit the scope of the invention as described in the claims.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.12/120,988 filed on 15 May 2008.

BACKGROUND OF THE INVENTION

The present invention relates to configurations for transferring signalsamples over data ports at the digital interface for multipleanalog-to-digital converters (ADCs), particularly for transferringsampled signal data at higher rates over fewer data ports at the digitalinterface.

A typical digital interface for multiple ADCs operating in parallelincludes the same number of data ports for transferring signal samples.Each ADC digitally samples a corresponding input analog signal at asample rate and a number of bits per sample, or sample width, to producethe signal samples. The bit rate is the product of the sample rate andthe number of bits per sample. In typical designs, the data transferrate of the data port is the same as the ADC bit rate. In flexible ADCsystems, the ADC can be configured to operate at a selected sample ratewithin a range of possible sample rates, often in response to anexternally supplied sample clock. The data ports can also operate atdifferent data transfer rates so that they match the ADC bit rates. Thebits of the signal samples are serialized and transmitted over the dataport at the same rate that they are generated but with a fixed latency.

In general, the sample rate of the ADC is set to at least the Nyquistrate for the input analog signal to produce samples free of aliasing.The Nyquist rate is two times the bandwidth of the input analog signal.In some situations, an input analog signal having a narrower bandwidthcan allow the sample rate of the ADC to be lower than the ADC's maximumsample rate. The data port connected to the ADC will transfer the bitsat a lower rate than the maximum data transfer rate. Even though theyare operating below capacity, the data ports often consume the sameamount of power. Furthermore, the number of I/O pins remains the same sothat the design complexity and related system costs are the same as whenthe bandwidth is fully utilized or when the ADCs are operating at theirmaximum rate.

An analogous situation exists for DAC interfaces. For example, signalsamples representing multiple signals that have been processed by adigital signal processor are transferred across a digital interface tomultiple DACs where they will be converted to multiple analog signals.The digital interface includes a data port for each DAC. When theproduct of the sample rate and number bits per sample results in a lowerbit rate than the maximum data transfer rate per port, there is excessdata transfer bandwidth at the digital interface. Again, there are powerconsumption, design complexity and system costs related to maintainingthe same number of data ports having unused bandwidth.

Another approach for transferring data from multiple ADCs or to multipleDACs is to serialize the signal samples for a high speed serial datalink. Existing industry standards such as PCI Express, aimed atmicroprocessors or interface devices, add overhead and complexity to theserialized data that are unnecessary for a simple continuous, constantbandwidth data stream. The industry standard entitled “JEDEC Standardfor Serial Interface for Data Converters JESD204,” published by theJEDEC Solid State Technology Association in April 2006, specifiesarchitectures and data formats for transfer of signal samples over highspeed serial data links between data converters and digital logicdevices, referred to as 8b/10b SerDes. The JEDEC Standard describesarranging the bits of signal samples into 8-bit data words. Each 8-bitdata word is mapped to a 10-bit symbol in accordance with an 8b/10b code(IEEE Standard 802.3-2002). The 10-bit symbols are then serialized fortransfer over the data link. For signal samples having a data widthgreater than 8 bits, the bits are sequentially arranged into 8-bit datawords. For instance, a 12-bit signal sample would have 8 bits in a firstword and 4 bits in a second word. The next 12-bit signal sample wouldhave 4 bits in the second word and 8 bits in a third word and so forth.For multiple ADCs or DACs in parallel, the bits of signal samplescorresponding to each ADC or DAC are arranged sequentially in a frame of8-bit data words, where a frame includes the data words generated duringone sample period. The 8b/10b encoding of each 8-bit word forms a frameof 10-bit symbols that are serialized and transferred over the datalink. On the receiver side, the received serial data stream isdeserialized to reconstruct the 10-bit symbols that are 8b/10b decodedto regenerate the 8-bit words of each frame. The bits corresponding tothe sample width of each signal sample are extracted from the 8-bitwords to reconstruct the signal samples for the corresponding ADC orDAC. The JEDEC Standard specifies a range of gross data transfer ratesfrom 0.3125 to 3.125 gigabits per second (Gbps).

The JEDEC SerDes architecture has the complexity and overhead of 8b/10bencoding at the transmit side and 8b/10b decoding at the receive side.The fixed 8-bit word size also adds complexity for data converters whosesample width is not equal to 8 bits and/or have multiple ADCs ormultiple DACs operating in parallel. The JEDEC SerDes architecture isapplicable to high speed serial data links for longer distances (up to20 cm at 3.125 Gbps), however it is more costly and requires more power.

In a system having multiple ADCs or multiple DACs, there is a need for adigital interface that increases power efficiency, reduces systemcomplexity and reduces the cost of the system. There is a need for adigital interface that exploits unused bandwidth of the data ports torealize these improvements.

SUMMARY OF THE INVENTION

Embodiments of the present invention have been made in consideration ofthe foregoing conventional problems. An object of the present inventionis to use fewer ports for data transfer at a digital interface of a dataconverter having multiple ADCs or multiple DACs.

To realize the foregoing object, one aspect of the present inventionprovides a method for transferring signal samples over a digitalinterface of a data converter implemented in a single integrated circuitincluding N ADCs, N analog inputs at an analog interface for receiving Nanalog signals, where N is greater than one, and at least one data portat the digital interface. The method comprises:

digitally sampling the N analog signals received at the analog interfaceof the integrated circuit, wherein the N ADCs respond to an input clockto form N signal samples per sample period, the input clock having aninput clock frequency, wherein each ADC produces one signal sample persample period in accordance with the input clock frequency, the signalsample represented by a number of bits per sample;

mapping the bits of the N signal samples for each sample period to Msubsets of bits to form M multiplexed data sets, where M is greater thanone and less than N, wherein each multiplexed data set consists of anumber K of multiplexed bits equal to the number of bits per samplemultiplied by N then divided by M;

generating a data clock having a data clock frequency substantiallyequal to the input clock frequency multiplied by the number K;

serializing the multiplexed bits of the M multiplexed data sets inresponse to the data clock to provide the K multiplexed bits of acorresponding multiplexed data set sequentially at the data clockfrequency to a corresponding data port of the plurality of data ports;and

transmitting the M multiplexed data sets in parallel over M of the dataports of the integrated circuit, wherein the corresponding data porttransmits the K multiplexed bits of the corresponding multiplexed dataset at a data transfer rate that depends on the data clock frequency.

Another aspect of the present invention that realizes the foregoingobject provides a multiple analog to digital converter apparatusimplemented in a single integrated circuit including N analog inputsthat receive N analog signals at an analog interface, where N is greaterthan one, and at least one data port at a digital interface. Theapparatus comprises:

N ADCs that digitally sample the N analog signals received at the analoginterface of the integrated circuit, wherein the N ADCs produce N signalsamples per sample period in response to an input clock, the input clockhaving an input clock frequency, wherein each ADC produces one signalsample per sample period in accordance with the input clock frequency,the signal sample represented by a number of bits per sample;

one or more multiplexers, each multiplexer receiving signal samples fromat least two ADCs and each ADC providing signal samples to one of themultiplexers, wherein the one or more multiplexers map the bits of the Nsignal samples for each sample period to M subsets of bits to form Mmultiplexed data sets in accordance with a predetermined mapping, whereM is greater than one and less than N, wherein each multiplexed data setconsists of a number K of multiplexed bits equal to the number of bitsper sample multiplied by N then divided by M;

a data clock having a data clock frequency substantially equal to theinput clock frequency multiplied by the number K, the data clockdistributed to a plurality of serializers; and

the plurality of serializers receiving the M multiplexed data sets fromthe one or more multiplexers and providing the M multiplexed data setsto M of the data ports, wherein a corresponding serializer receives acorresponding multiplexed data set and responds to the data clock toprovide the K multiplexed bits sequentially at the data clock frequencyto a corresponding data port, the corresponding data port transmittingthe K multiplexed bits of the corresponding multiplexed data set at adata transfer rate that depends on the data clock frequency, wherein theM data ports transmit the multiplexed data sets in parallel from theintegrated circuit.

Another aspect of the present invention that realizes the foregoingobject provides a multiple analog to digital converter apparatusimplemented in a single integrated circuit including N analog inputsthat receive N analog signals at an analog interface, where N is greaterthan one, and at least one data port at a digital interface. Theapparatus comprises:

N ADCs operating in parallel to digitally sample the N analog signalsreceived at the analog interface of the integrated circuit to form Nsignal samples per sample period, wherein each ADC operates at a samplerate to produce one signal sample per sample period, the signal samplerepresented by a number of bits per sample such that the ADC producesbits at an ADC bit rate;

one or more multiplexers, each multiplexer receiving signal samples fromat least two ADCs and each ADC providing signal samples to one of themultiplexers, wherein the multiplexer maps the bits of the N signalsamples for each sample period to M subsets of bits to form Mmultiplexed data sets in accordance with a predetermined mapping, whereM is greater than one and less than N, wherein each multiplexed data setincludes a number of multiplexed bits equal to the number of bits persample multiplied by N then divided by M; and

M serializers, wherein each serializer receives a correspondingmultiplexed data set and provides the multiplexed bits sequentially to acorresponding data port, the corresponding data port transmitting themultiplexed data set provided by the serializer at a data transfer ratethat is greater than the ADC bit rate, wherein the M of the data portstransmit the M multiplexed data sets in parallel from the integratedcircuit.

Another object of the present invention is to use fewer data ports fordata transfer between a source device providing multiple digital signalsand a data converter having multiple DACs. To realize the foregoingobject, one aspect of the present invention provides a method oftransferring N digital signals from a source device to a data converter,wherein each digital signal is represented by a plurality of signalsamples having a sample rate and a number of bits per sample, the sourcedevice having at least one output data port, the data converterimplemented in a single integrated circuit including N DACs, at leastone input data port at a digital interface and N analog outputs at ananalog interface. The method comprises:

mapping the bits representing the N signal samples for each sampleperiod to M subsets of bits in accordance with a predetermined mappingto form M multiplexed data sets at the source device, where M is greaterthan one and less than N, wherein each multiplexed data set includes anumber of multiplexed bits equal to the number of bits per samplemultiplied by N then divided by M;

transmitting the M multiplexed data sets in parallel over M of theoutput data ports of the source device, wherein each output data porttransmits a corresponding multiplexed data set at a data transfer ratethat is greater than the sample rate multiplied by the number of bitsper sample;

receiving the M multiplexed data sets over M of the input data ports atthe digital interface of the integrated circuit, wherein each input dataport receives a corresponding multiplexed data set at the data transferrate;

reordering the M multiplexed data sets to reproduce a set of the Nsignal samples in parallel, wherein the N signal samples are producedduring each sample period, wherein the reordering is an inverse mappingof the predetermined mapping at the source device;

providing consecutive sets of N signal samples corresponding toconsecutive signal samples of the N digital signals to the N DACs, eachDAC receiving the consecutive signal samples of a corresponding digitalsignal;

converting the consecutive signal samples of the N digital signals to Nanalog signals, each DAC converting the consecutive signal samples to acorresponding analog signal at the sample rate; and

providing the N analog signals to the N analog outputs at the analoginterface of the integrated circuit.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1A is a block diagram of a parallel ADC system, in accordance withthe prior art.

FIG. 1B illustrates the arrangement of the output bits during one sampleperiod for the system of FIG. 1A, in accordance with the prior art.

FIG. 2A is a block diagram of a data converter system configuration thatincludes twelve data ports for transferring data from sixteen ADCs.

FIG. 2B illustrates the arrangement of bits provided to the data portsduring one sample period for the embodiment of FIG. 2A.

FIG. 3A is a block diagram of a data converter system configuration thatincludes eight data ports for transferring data from sixteen ADCs.

FIG. 3B illustrates the arrangement of bits provided to the data portsduring one sample period for the configuration of FIG. 3A.

FIG. 4A is a block diagram of a data converter system configuration thatincludes six data ports for transferring data from sixteen ADCs.

FIG. 4B illustrates the arrangement of bits provided to the data portsduring one sample period for the embodiment of FIG. 4A.

FIG. 5A is a block diagram of a data converter system configuration thatincludes four data ports for transferring data from sixteen ADCs.

FIG. 5B illustrates the arrangement of bits during one sample period forthe embodiment of FIG. 5A.

FIG. 6A is a block diagram of a reconfigurable data conversion system.

FIG. 6B shows a table of operating modes for the configurable system ofFIG. 6A.

FIG. 7 is a block diagram of the host device that is the destination ofthe transmitted bit streams.

FIG. 8A is a block diagram of an application device that includes portconcentration for efficient data transfer.

FIG. 8B is a block diagram of the digital to analog conversion devicethat includes port concentration.

DETAILED DESCRIPTION

FIG. 1A is a block diagram of a parallel ADC system in accordance withthe prior art. This system includes sixteen channels for digitizingsixteen analog signals, each channel including an ADC 110 i and a dataport 130 i. The number of channels can be different depending on thesignal processing application. The ADCs 110 digitally sample a pluralityof input analog signals (not shown) in parallel to produce a pluralityof signal samples at the ADC outputs 112 during each sample period. EachADC 110 i samples the corresponding input analog signal at the samplerate. The sample period is the inverse of the sample rate. The signalsample at each ADC output 112 i has a sample width of twelve bits persample. The plurality of serializers 120 arranges the bits of eachsignal sample in sequential order, where the most significant bit (MSB)is first or the least significant bit (LSB) is first in accordance withuser control (not shown). Each serializer 120 i provides its sequence ofbits to a corresponding data port 130 i. The data ports 130 produceoutputs 132 for transfer across I/O pins (not shown). For this example,the data ports 130 are low voltage differential signaling (LVDS) ports,described further below. The ADC input clock 150 provided by a hostsystem has a clock frequency corresponding to the sample rate. The ADCs110 respond to the ADC input clock 150 to sample the input analogsignals at the sample rate. The phase lock loop (PLL) 160 operates onthe ADC input clock to produce a data clock 161 for the serializers 120and the data ports 130. The data clock frequency corresponds to the datatransfer rate of the bits output from each serializer 120 i. The dataclock frequency is the ADC clock frequency multiplied by the number ofbits per sample, in this case twelve, so the data transfer rate is thesame as the ADC bit rate. The data clock frequency is divided by twelveto provide a frame clock 162. The frame clock 162 indicates the timingof output data frames, where one frame includes a data word for eachchannel. In this case, the data word includes the serialized bitsrepresenting one signal sample. Input data ports at a host devicereceive the frames of bits using a corresponding number of LVDS portsoperating in parallel and reproduce each signal sample, as describedbelow with respect to FIG. 7.

The data ports 130 provide low voltage differential signaling (LVDS)data transmission. The document entitled “LVDS Owner's Manual IncludingHigh-Speed CML and Signal Conditioning”, Fourth Edition, published inJanuary 2008 by National Semiconductor describes LVDS devices andarchitectures. The LVDS data transmission has desirable characteristics,including a maximum data transfer rate of 3.125 Gbps, low noise and lowpower consumption. The differential signaling requires two I/O pins perchannel output 132 i, one for the positive differential output and onefor the negative differential output, referred to as an LVDS pair. Atthe host device, the input data ports are LVDS receivers. The LVDSreceiver responds to the received differential signal to generate logicstates corresponding to the bits of the signal samples.

FIG. 1B illustrates the arrangement of the output bits during one sampleperiod for the system of FIG. 1A. The table 170 represents the sequenceof bits output from the sixteen data channels during one sample period.Line 170 i represents the twelve serialized bits of a sample generatedby the i^(th) ADC 110 i that form the input to the i^(th) data port 130i. For example ADC5[11:0] represents the serialized 12 bits of thesample output from ADC 110 i (ADC5) during one sample period. Since thedata transfer rate is 12 times the sample rate, the transfer period perbit is the sample period divided by 12.

The data ports 130 i will have excess bandwidth when the product of thesample rate and number of bits per sample results in an ADC bit ratethat is lower than the maximum data transfer rate. For example in FIG.1A, suppose the ADC clock frequency is 50 megahertz (MHz), correspondingto 50 megasamples/second (Msps), and the sample width is 12 bits persample so that each ADC 110 i produces 600 megabits per second (Mbps).The data transfer rate will be 600 Mbps for each data port 130 i. For anLVDS port having a maximum data transfer rate of 800 Mbps, there is anunused bandwidth of 200 Mbps for each port. The LVDS ports 130 willconsume the same amount of power to transfer data at 600 Mbps as theywould for transferring data at full capacity of 800 Mbps.

The present invention exploits this excess data transfer capacity bycombining bits from multiple ADC outputs and transmitting the combineddata at a faster rate over fewer ports. Each data port transmits thecombined data at a rate that is greater than the ADC bit rate and up tothe maximum data transfer rate. For the above example, the signalsamples output from the sixteen ADCs 110 at an ADC bit rate of 600 Mbpscan be combined into twelve bit streams, each with a bit rate of 800Mbps. Twelve of the sixteen ports would transfer the twelve combined bitstreams, each at the maximum data transfer rate of 800 Mbps (800Mbps×12=600 Mbps×16). Depending on the sample rate, the number of bitsper sample and the maximum data transfer rate, several configurationsare possible. FIGS. 2A,B to 5A,B show alternative configurations forsystems having sixteen ADCs, twelve bits per sample and 800 Mbps maximumdata transfer rate for each port. FIGS. 2A,B apply to sample rates up to50 MHz, FIGS. 3A,B apply to sample rates up to 33 MHz, FIGS. 4A,B applyto sample rates up to 25 MHz and FIGS. 5A,B apply to sample rates up to16.6 MHz. These system configurations are exemplary and do not limit thescope of the present invention as described in the claims. The presentinvention also applies to configurations having different numbers ofADCs, sample widths and maximum data transfer rates.

FIG. 2A is a block diagram of a system configuration that includestwelve data ports for transferring data from sixteen ADCs. Thisconfiguration can accommodate sample rates up to 50 Msps correspondingto ADC clock frequencies up to 50 MHz. The multiplexers 210 receive thesignal samples output from the ADCs 110. Four ADCs 110 h, 110 i, 110 jand 110 k provide signal samples to one multiplexer 210 i. Themultiplexer 210 i includes three outputs 212 i, 212 j and 212 k. Themultiplexer 210 i reorders the 48 bits of the samples it receives duringeach sample period and distributes the reordered bits to threeserializers 220 i, 220 j and 220 k. Each serializer 220 i, 220 j and 220k receives a subset of the 48 reordered bits, in this case 16 bits, andserializes them for transfer by a corresponding port 230 i, 230 j and230 k. The PLL 260 produces the data clock 261 having a frequency thatis 16 times the ADC clock frequency. The frame clock 262 corresponds toframes having 16-bit data words. The twelve ports 230 transfer theserialized bits at a data transfer rate that is 16 times the samplerate. In contrast, the system of FIG. 1A includes 16 data ports 130 totransfer the serialized bits at a data transfer rate that is 12 timesthe sample rate and frames having 12-bit data words.

FIG. 2B illustrates the arrangement of bits provided to the data ports230 during one sample period for the embodiment of FIG. 2A. Table 270depicts the bit mapping of the sample bits output from the sixteen ADCsduring one sample period. For the configuration having four multiplexers210 and three serializers 220, the multiplexers 210 group the bits ofeach signal sample into blocks of 4 bits. The multiplexer 210 i directsthe first block of bits to the serializer 220 i, the second block ofbits to the serializer 220 j and the third block of bits to theserializer 220 k. Lines 270 i, 270 j and 270 k represent the bit mappingfor serializers 220 i, 220 j and 220 k, respectively. Other bit mappingsresulting in different bit orders can be used provided that each of theserializers 220 outputs sixteen mapped bits during one sample period.The host device reorders the received multiplexed bits in accordancewith the inverse bit mapping to restore the original signal samples.

FIG. 3A is a block diagram of a system configuration that includes eightdata ports for transferring data from sixteen ADCs. This configurationcan accommodate sample rates up to 33.3 Msps corresponding to ADC clockfrequencies up to 33.3 MHz. For sample rates in this range, the bits ofthe signal samples from the ADCs 110 can be multiplexed to form eightbit streams. The multiplexers 310 provide bit streams to eightserializers 320 for transfer over eight data ports 330. During onesample period, the multiplexer 310 i receives two signal samples inparallel from ADCs 110 i and 110 j and provides a single stream of 24consecutive bits to the serializer 320 i. The serializer 320 i providesthe multiplexed bits to the data port 330 i. The PLL 360 produces thedata clock 361 having a frequency that is 24 times the ADC clockfrequency. The frame clock 362 corresponds to frames having 24-bit datawords. The data ports 330 respond to the data clock 361 to transfer theserialized bits at a data transfer rate that is 24 times the samplerate. When the sample rate is 33 MHz, the data transfer rate is 792Mbps.

FIG. 3B illustrates the arrangement of bits provided to the data ports330 during one sample period for the configuration of FIG. 3A. Table 370depicts the bit mapping of the sample bits output from the sixteen ADCsduring one sample period. The multiplexer 310 i provides 24 bitsincluding the twelve bits of the signal sample from ADC 110 i followedby the twelve bits of the signal sample from ADC 110 j, as shown in line370 i. Again, other bit mappings are possible as long as the multiplexer310 i provides 24 bits during one sample period.

FIG. 4A is a block diagram of a system configuration that includes sixdata ports for transferring data from sixteen ADCs. This configurationcan accommodate sample rates up to 25 Msps corresponding to ADC clockfrequencies up to 25 MHz. For sample rates in this range, the bits ofthe signal samples from the ADCs 110 can be multiplexed into six bitstreams. The multiplexers 410 provide bit streams to six serializers 420for transfer over six data ports 430. During one sample period, eachmultiplexer 410 i combines bits from eight signal samples to form threestreams, each with 32 multiplexed bits. Each serializer 420 i providesmultiplexed bits to the corresponding data port 430 i. The PLL 460produces the data clock 461 having a frequency that is 32 times the ADCclock frequency. The frame clock 462 corresponds to frames having 32-bitdata words. The data ports 430 transfer the serialized bits at a datatransfer rate that is 32 times the sample rate. For a sample rate of 25MHz, the data transfer rate is 800 Mbps.

FIG. 4B illustrates the arrangement of bits provided to the data ports430 during one sample period for the embodiment of FIG. 4A. Table 470depicts the bit mapping of the signal samples output from the ADCs 110during one sample period. For the configuration having two multiplexers410 and six serializers 420, each multiplexer 410 groups the bits ofeach signal sample into blocks of 4 bits. The multiplexer 410 i directsthe first block of bits to the serializer 420 i, the second block ofbits to the serializer 420 j and the third block of bits to theserializer 420 k. Lines 470 i, 470 j and 470 k represent the bit ordersfor serializers 420 i, 420 j and 420 k, respectively. Again, other bitmappings are possible.

FIG. 5A is a block diagram of a system configuration that includes fourdata ports for transferring data from sixteen ADCs. This configurationcan accommodate sample rates up to 16.6 Msps corresponding to ADC clockfrequencies up to 16.6 MHz. For sample rates in this range, the bits ofthe signal samples from the ADCs 110 can be multiplexed into four bitstreams. Two multiplexers 510 provide bit streams to four serializers520 for transfer over four data ports 530. During one sample period,each multiplexer 510 i combines bits from eight signal samples to formtwo streams, each having 48 multiplexed bits. Each serializer 520 iprovides the multiplexed bit stream to the corresponding data port 530i. The PLL 560 produces the data clock 561 having a frequency that is 48times the ADC clock frequency. The frame clock 562 corresponds to frameshaving 48-bit data words. The data ports 530 each transfer theserialized bits at a data transfer rate that is 48 times the samplerate.

FIG. 5B illustrates the arrangement of bits during one sample period forthe embodiment of FIG. 5A. Table 570 depicts the bit mapping of signalsamples output from the sixteen ADCs 110 during one sample period. Forthe configuration having two multiplexers 510 and four serializers 520,each multiplexer 510 i arranges the bits from eight signal samples asshown in lines 570 i and 570 j. The multiplexer 510 i directs the streamof bits shown in line 570 i to the serializer 520 i and the stream ofbits shown in line 570 j to the serializer 520 j. Again, other bitmappings are possible.

FIG. 6A is a block diagram of a reconfigurable data conversion system.This system is adaptable to operate in modes associated with theconfigurations of FIGS. 1A,B to FIGS. 5A,B. The N ADCs 110 digitallysample N input analog signals (not shown) to produce signal samplesrepresented by x₁ to x_(N). The reconfigurable multiplexer 610 reordersthe bits of the signal samples x₁ to x_(N) into M multiplexed bitstreams y₁ to y_(M). The reconfigurable serializer 620 serializes eachmultiplexed bit stream y_(i). The controller 640 enables M of the dataports 630 to transmit the multiplexed bit streams. The controller 640responds to user input 650 to provide control parameters appropriate forthe operating mode. These modes are referred to herein as a normal mode(M=N), one or more port concentration modes (1<M<N) and a serial mode(M=1). The configurable data conversion system includes the ADC inputclock, data clock, frame clock and PLL operating as previously describedwith respect to FIGS. 1A to 5A, but not shown in FIG. 6A. The controller640 provides control parameters to set the frequencies for the clocks inaccordance with the selected operating mode. In this description for theconfigurable system of FIG. 6A, it is assumed that the system hassixteen ADCs 110 providing 12 bits per sample, sixteen data ports 630and a maximum data transfer rate of 800 Mbps. This example does notlimit the scope of the present invention as described in the claims.

The normal mode corresponds to FIGS. 1A and 1B. The normal mode enablesconventional operation, where the N data ports 630 transfer the signalsamples at the ADC bit rate. The number of active data ports M equalsthe number of available data ports N. The controller 640 enables directconnections from the ADCs 110 to the serializers 620, so that the ADCs110 provide the signal samples directly to the serializers 620. Thecontroller 640 enables N active data ports 630. The normal mode can beused for any sample rate supported by the ADCs 110 and the data ports630, but is necessary when the ADC bit rate that is at or near themaximum data transfer rate. For example, a sample rate of 65 MHz resultsin an ADC bit rate of 780 Mbps. This ADC bit rate is sufficiently nearthe maximum data transfer rate of 800 Mbps that all sixteen of the dataports 630 are used for data transfer.

The port concentration modes correspond to configurations that use M ofthe N data ports 630, where 1<M<N. The operations of the portconcentration modes correspond to FIGS. 2A,B to FIGS. 5A,B. The user canspecify control parameters indicating the particular port concentrationmode, the ADC clock rate, the data clock rate and the disabled LVDSports. The controller 640 applies the control parameters to adapt theADCs 110, multiplexer 610, serializer 620 and data ports 630 to operatein accordance with user's specifications. The controller 640 enablesactive data ports and powers down the unused ports. For example toconfigure the system to operate as shown in FIG. 2A having a sample rateof 50 MHz, the controller 640 configures the multiplexer 610 and theserializer 620 to generate 12 multiplexed bit streams (M=12) for the 12active data ports while the remaining four data ports are powered down.The frequency of sample clock 150 (not shown in FIG. 6A) is set to 50MHz. The ADCs 110 respond to the sample clock to sample the input analogsignals at 50 Msps. The reconfigurable multiplexer 610 and theserializer 620 respond to the control parameters to reorder the bits ofthe signal samples as described with respect to FIG. 2B and providetwelve multiplexed bit streams corresponding to the twelve active dataports. The controller also provides timing control parameters to a PLL(not shown in FIG. 6) so that the data clock frequency and frame clockfrequency are appropriate for the operating mode, which for this examplecorresponds to PLL 260 in FIG. 2A. At a host device, the transmitted bitstreams are received by twelve data ports and are demultiplexed toreproduce the sixteen signal samples for each sample period.

FIG. 6B shows a table of operating modes for the configurable system ofFIG. 6A. The configurable system in this example includes five operatingmodes. The normal mode, corresponding to FIGS. 1A and 1B, is selectablefor ADC frequencies from 10 to 65 MHz, the data clock frequency is 12times the ADC clock frequency and the number of active data ports is 16.Note that for ADC clock frequencies below 50 MHz, the normal mode isless efficient than the port concentration modes because it uses moreactive data ports. For each port concentration mode, the correspondingrange of the ADC clock frequencies allows the most efficientconfiguration using the fewest number of active data ports. Any portconcentration mode can be applied to ADC clock frequencies that are lessthan lower boundary of the range indicated, however more than thenecessary number of data ports will be active. The data clock frequencyfactor is multiplied by the ADC clock frequency to give the data clockfrequency corresponding to the data transfer rate. The values given inFIG. 6B correspond to the example of a system including sixteen ADCs,sample rates up to 65 Msps with twelve bits per sample and maximum datatransfer rate of 800 Mbps. Other applications having different systemparameters can have different configurations for the operating modes.

For sufficiently low sample rates, the configurable system of FIG. 6Acan operate in the serial mode (M=1). In the serial mode, themultiplexer 610 combines the bits of all the signal samples outputduring each sample period to produce a single multiplexed bit stream.The controller 640 enables one active data port and powers down theremaining unused ports. For example, when the system of FIG. 6A has asample rate of 4 MHz, the controller 640 configures the multiplexer 610and the serializer 620 to serialize the bits of the N signal samplesduring each sample period to generate one serialized data set. The oneactive data port transmits the serial data sets as a single serial datastream at a data transfer rate of 768 bps, or 192 times the sample rate.In general, a configurable system can operate in the serial mode whenthe product of the sample rate, sample width and the number of ADCs isless than or equal to the maximum data transfer rate of one data port.

FIG. 7 is a block diagram of the host device that is the destination ofthe transmitted bit streams. When the data conversion system transmitsthe bit streams in a port concentration mode, the host device requiresfewer input data ports 710, resulting in power savings and reducedcomplexity. The input data ports 710 are LVDS receivers. Each LVDSreceiver receives the differential signal produced by LVDS transmissionand generates a logic state that reproduces the corresponding bits. Thedeserializer 715 converts the received serial bits to parallelmultiplexed bit streams y₁ to y_(M). A demultiplexer 720 rearranges thebits of the received multiplexed bit streams y₁ to y_(M) to the order ofthe original signal samples x₁ to x_(N). The application processor 730stores or processes the signal samples x₁ to x_(N) in accordance withthe application-specific functions of the host device. The host devicecan also be configurable for different operating modes, analogous tothose described for the configurable data converter system of FIG. 6A.The configurable host device can include up to N input data ports 710,where M input data ports are enabled to receive the multiplexed bitstreams. A controller (not shown) would respond to user input to enablethe M input data ports, power down the remaining input data ports andconfigure the demultiplexer 720 to invert the mapping of the multiplexer610.

Another embodiment of the present invention provides efficienttransmission of digital signals from an application device to a digitalto analog conversion device. FIG. 8A is a block diagram of anapplication device that includes port concentration for efficient datatransfer. The application device includes an application processor 810that generates N digital signals. The configurations for portconcentration are analogous to those described above for the dataconverter system, except that signal samples, x₁ to x_(N) correspond toone sample from each digital signal output from the applicationprocessor 810 instead of N ADCs 110. The signal samples have a samplerate and the signal samples x₁ to x_(N) are parallel samples providedduring one sample period. The multiplexer 820 and the serializer 830provide multiplexed bit streams y₁ to y_(M). A reduced number M of dataports 840 transmit the multiplexed bit streams y₁ to y_(M) to thedigital to analog converter device. The application device can also beconfigured for selectable operating modes, including normal, portconcentration and serial modes, by incorporating a controller such asthat described with respect to FIG. 6A. The application device alsoincludes a data clock, frame clock, PLL and a sample clock instead of anADC input clock, analogous to those described with respect to FIGS. 1Ato 5A. The controller provides control parameters to set the frequenciesfor the clocks in accordance with the selected operating mode. FIG. 8Bis a block diagram of the digital to analog conversion device. At thedigital interface of the DAC device, M data ports 850 receive the bitstreams and the deserializer 855 converts the received serial bits toparallel multiplexed bit streams y₁ to y_(M). During each sample period,the demultiplexer 860 reorders the bits of the multiplexed bit streamsy₁ to y_(M) to reproduce the signal samples x₁ to x_(N) of the N digitalsignals. The N DACs 870 convert the N digital signals to N analogsignals (not shown). The DAC device can also be configurable for theport concentration modes, normal mode and serial mode. The configurableDAC device can include up to N input data ports 850, where M input dataports are enabled to receive the multiplexed bit streams. A controller(not shown) would respond to user input to enable the M input dataports, power down the remaining input data ports and configure thedemultiplexer 860 to invert the mapping of the multiplexer 820.

The embodiments described above include multiplexers that reorder thebits of the output samples of the parallel ADCs. A typical multiplexeris a data selector having multiple inputs and an output. The multiplexerselects from among the data inputs based on one or more input controlsignals. Logic circuitry applied to the data inputs and the controlsignals selects a particular input to produce the output. Alternativesfor the multiplexers shown in FIGS. 2A,B to 8A,B may have differentconfigurations and connections with the parallel ADCs. Various orders ofthe reordered bits, shown in FIGS. 2B to 5B, may be used to produce thesame number of output bit streams. A FIFO buffer can be coupled betweenthe multiplexers and the serializers. The multiplexer outputs arewritten to the buffer at the ADC clock frequency and provided to theserializers at a rate compatible with the data clock frequency. Themultiplexers and the timing of accesses to the FIFO buffers provide thereordered bits in the appropriate order to the serializers. Inalternative embodiments, various devices may be used to reorder the bitsoutput from the ADC to produce a reduced number of data streams.

An ADC system incorporating the present invention can be implemented ina single integrated circuit (IC) having N analog inputs and at least MLVDS data ports. The IC includes N independent ADCs for converting Ninput analog signals to N digital signals in parallel. The ADCs can beimplemented by pipeline data converters comprising multiple stages offlash converters, although the present invention is applicable to otherADC architectures. The resulting signal samples are passed to digitallogic implementing the multiplexers and serializers for reordering thebits of the signal samples. The M multiplexed bit streams are providedto the LVDS pairs for low pin count, low noise interface to the hostprocessor. For operating in a single mode, the number of active dataports is a fixed value of M (where M>1) based on system specifications.For configurable operation in more than one mode, such as described withrespect to FIGS. 6A and 6B, the ADC system includes up to N data ports.Input for the controller 640 can be implemented using I/O pinsdesignated for control parameter input and/or a configuration register.Serial peripheral interface (SPI) pins can provide the controlparameters to the control register. For the host device described withrespect to FIG. 7, the data ports 710 and demultiplexer 720 areintegrated with the device, reducing the number of required data portsfrom N to M. A configurable host device would also include thecontroller to support multiple port concentration modes.

For the application device, such as described with respect to FIG. 8A,the multiplexer, serializer and controller are integrated within thedevice for transferring samples of the N digital signals over M dataports of the device. The DAC system described with respect to FIG. 8Bcan be implemented in a single IC that includes N DACs 870 forconverting N digital signals to N analog signals, at least M data ports850 for receiving multiplexed bit streams and a demultiplexer 860 forconverting the M multiplexed bit streams to N signal samples of Ndigital signals per sample period. The implementation of a configurableDAC device also includes the controller (not shown in FIG. 8B) withinthe device to support the different port concentration modes.

The embodiments described above include LVDS data ports. Other dataports and transmission protocols can be used for transfer of themultiplexed bit streams. Alternative embodiments can include 8b/10bSerDes or other encoding/decoding. For example, the buffering andcontrol logic required for 8b/10b encoding can be added to theserializers on the transmit side and 8b/10b decoding can be added to thedeserializers on the receive side.

The components described for these embodiments are meant to be exemplaryonly and are not intended to limit the invention to any specific set ofcomponents or configurations. In various embodiments, one or more of thecomponents described may be omitted, combined, modified, or additionalcomponents may be included.

While the preferred embodiments of the invention have been illustratedand described, it will be clear that the invention is not limited tothese embodiments only. Numerous modifications, changes, variations,substitutions and equivalents will be apparent to those skilled in theart, without departing from the spirit and scope of the invention, asdescribed in the claims.

1. A method of transferring signal samples over a digital interface of adata converter implemented in a single integrated circuit including Nanalog to digital converters (ADCs), N analog inputs at an analoginterface for receiving N analog signals, where N is greater than one,and a plurality of data ports at the digital interface, the methodcomprising: digitally sampling the N analog signals received at theanalog interface of the integrated circuit, wherein the N ADCs respondto an input clock to form N signal samples per sample period, the inputclock having an input clock frequency, wherein each ADC produces onesignal sample per sample period in accordance with the input clockfrequency, the signal sample represented by a number of bits per sample;mapping the bits of the N signal samples for each sample period to Msubsets of bits to form M multiplexed data sets, where M is greater thanone and less than N, wherein each multiplexed data set consists of anumber K of multiplexed bits equal to the number of bits per samplemultiplied by N then divided by M; generating a data clock having a dataclock frequency substantially equal to the input clock frequencymultiplied by the number K; serializing the multiplexed bits of the Mmultiplexed data sets in response to the data clock to provide the Kmultiplexed bits of a corresponding multiplexed data set sequentially atthe data clock frequency to a corresponding data port of the pluralityof data ports; and transmitting the M multiplexed data sets in parallelover M of the data ports of the integrated circuit, wherein thecorresponding data port transmits the K multiplexed bits of thecorresponding multiplexed data set at a data transfer rate that dependson the data clock frequency.
 2. The method of claim 1, wherein theplurality of data ports at the digital interface consists of M dataports, wherein each data port is used for the step of transmitting. 3.The method of claim 1, the plurality of data ports includes more than Mdata ports, the method further comprising: enabling the number M of theplurality of data ports, wherein remaining data ports in the pluralityof data ports are powered down.
 4. The method of claim 1, wherein thedata ports in the plurality of data ports comprise low voltagedifferential signaling (LVDS) ports, wherein the step of transmittingtransfers the multiplexed data sets over M LVDS ports.
 5. The method ofclaim 1, further comprising: receiving the M multiplexed data sets inparallel at M input data ports of a destination device; and demappingthe multiplexed bits of the M multiplexed data sets to reproduce the Nsignal samples at the destination device.
 6. A multiple analog todigital converter (ADC) apparatus, implemented in a single integratedcircuit including N analog inputs that receive N analog signals at ananalog interface, where N is greater than one, and a plurality of dataports at a digital interface, the apparatus comprising: N ADCs thatdigitally sample the N analog signals received at the analog interfaceof the integrated circuit, wherein the N ADCs produce N signal samplesper sample period in response to an input clock, the input clock havingan input clock frequency, wherein each ADC produces one signal sampleper sample period in accordance with the input clock frequency, thesignal sample represented by a number of bits per sample; one or moremultiplexers, each multiplexer receiving signal samples from at leasttwo ADCs and each ADC providing signal samples to one of themultiplexers, wherein the one or more multiplexers map the bits of the Nsignal samples for each sample period to M subsets of bits to form Mmultiplexed data sets in accordance with a predetermined mapping, whereM is greater than one and less than N, wherein each multiplexed data setconsists of a number K of multiplexed bits equal to the number of bitsper sample multiplied by N then divided by M; a data clock having a dataclock frequency substantially equal to the input clock frequencymultiplied by the number K, the data clock distributed to a plurality ofserializers; and the plurality of serializers receiving the Mmultiplexed data sets from the one or more multiplexers and providingthe M multiplexed data sets to M of the data ports, wherein acorresponding serializer receives a corresponding multiplexed data setand responds to the data clock to provide the K multiplexed bitssequentially at the data clock frequency to a corresponding data port,the corresponding data port transmitting the K multiplexed bits of thecorresponding multiplexed data set at a data transfer rate that dependson the data clock frequency, wherein the M data ports transmit themultiplexed data sets in parallel from the integrated circuit.
 7. Theapparatus of claim 6, wherein the plurality of data ports at the digitalinterface consists of M data ports.
 8. The apparatus of claim 6, whereinthe plurality of data ports at the digital interface includes more thanM data ports, the apparatus further comprising: a controller coupled tothe plurality of data ports, wherein the controller enables M of theplurality of data ports, wherein remaining data ports are powered down.9. The apparatus of claim 6, wherein the plurality of data ports at thedigital interface includes more than M data ports, and the apparatusfurther comprising: a controller and a user input for receiving controlparameters from a user, wherein the controller responds to the userinput to select an operational mode from a plurality of selectableoperational modes, to enable M of the plurality of data ports and topower down remaining data ports, in accordance with the controlparameters.
 10. The apparatus of claim 6, wherein the plurality of dataports are coupled to M input data ports of a destination device, the Minput data ports receiving the M multiplexed data sets in parallel.